The present invention generally relates to a dual-diameter electrical conductor for use as an embedded plug in a microelectronic device, and to a method for fabricating such a conductor, and more particularly relates to a dual-diameter electrical conductor consisting of a lower body portion and an upper neck portion wherein the neck portion is fabricated with a diameter smaller than the lithographically defined diameter of the body portion, and to a method for fabricating such an electrical conductor by building insulating sidewall spacers to define the neck portion of the conductor. The use of this dual-diameter plug geometer provides a misalignment tolerance wherein the body portion of the plug is protected from exposure to subsequently deposited materials and process ambients when only the neck portion of the plug is completely overlapped by a subsequentially deposited conductor.
In modem microelectronic devices, dynamic random access memory (DRAM) devices have been widely used for fast and temporary data storage. In DRAM devices, small dimensions and high capacitance value per unit area of the capacitor memory cell are desirable characteristics for achieving a high storage density. A DRAM device is termed dynamic because the cells retain information only for a limited period of time and must be read and refreshed periodically, in contrast to a static random access memory (SRAM) cell which does not require periodic refresh signals in order to retain stored data.
A typical DRAM cell is formed by a field effect transistor and a storage capacitor. When DRAM cells were first developed, large footprint planar type storage capacitors were utilized. As the dimensions of modem memory devices continue to shrink, other capacitor designs with reduced chip real estate usage such as the stacked capacitor became important. In a stacked capacitor, the capacitor is generally formed vertically under a bit line on the surface of a silicon substrate. For a given capacitor footprint, storage capacitor area, and thus capacitance, can be increased by increasing the capacitor height. A stacked capacitor can be formed by a layer of a dielectric material such as silicon dioxide or oxide-nitride-oxide sandwiched between two layers of doped polysilicon.
Stacked capacitors for DRAMS are also built on substrates that contain embedded contact vias which are filled with a conductive plug material. The conductive plug connects a conductive element in the underlying substrate to an overlying bottom or stacked electrode. The conductive plug typically has a diameter that is equal to the minimum lithographic dimension. In the fabrication process for the stacked capacitor, a small amount of misalignment between the conductive plug and the stacked electrode can be tolerated. However, problems are encountered when the electrode fails to completely cover the plug. The problems caused by the misalignment are particularly serious for capacitors incorporating noble metal electrodes and high epsilon dielectrics. For example, the exposed plug material may oxidize during a subsequent dielectric material deposition process, to produce an insulating material or undesirable volume-change-induced stresses.
Alternatively, exposed plug material may also react with the subsequently deposited high epsilon dielectric, or produce a high-leakage path over the areas where the plug and high epsilon dielectric are in contact. Another consideration related to misalignment tolerance is the critical need to avoid the situation where a single electrode contacts two plugs. This can occur when a severe misalignment is coupled with an etch bias sufficient to enlarge the plug dimensions to the point that the separation between the edges of two adjacent plugs is smaller than the electrode diameter. This etch bias can be corrected by utilizing sidewall spacers inside the contact via hole.
A conventional capacitor electrode/contact plug structure is shown in FIG. 1. The microelectronic structure 10 is built on a silicon substrate 12 which has an active circuit element 14 formed in its top surface 16. On the top surface 16 of the substrate 12, a dielectric material layer 18 is first deposited and then a contact hole 22 is formed therein. Into the contact hole 22, either one or two conductive materials, such as conductive material 24 and 26 shown in FIG. 1, can be deposited and etched to form the contact plug 28. In a process where a stacked capacitor is to be formed, a layer of electrode material is then deposited on top of the dielectric layer 18 and the contact plug 28 and then formed into a conductive electrode 30. The conductive electrode 30 is formed by a standard lithographic method which typically has a minimum lithography dimension similar to the diameter of the contact plug 28. Due to an inevitable misalignment occurring in the lithography process, the electrode 30 overlaps the contact plug 28 on only about two thirds of its top surface and thus leaves about one third of its top surface uncovered or exposed. In a subsequent dielectric deposition process for forming the capacitor dielectric layer wherein high temperature is normally required, the uncovered surface area 32 of the contact plug 28 oxidizes and may become insulating. This provides an undesirable process element for the dielectric layer forma.
As device dimensions continue to shrink in large memory arrays, the spacings between adjacent plug/stacked electrode structures become closer together and as a consequence, the tolerance for misalignment between the plug and the stacked electrode lithography levels decreases. Reducing the required margin for misalignment tolerance (and thus the minimum required electrode diameter) would allow more space between electrodes having the-same center-to-center spacing. The extra spacing achieved can be used to better accommodate the dielectric and counter electrode layers which are subsequently deposited for the capacitor that must fit between adjacent electrodes. Alternatively, reducing the minimum required electrode diameter would allow smaller footprint capacitors with the smaller center-to-center spacing expected to be necessary for the reduced wiring dimensions and cell sizes in larger than 4 gigabit DRAM. One way to achieve a reduced minimum electrode diameter is to utilize sidewall spacers inside a contact via hole.
Insulating sidewall spacers have been used in semiconductor structures, however, they are typically formed on the outer surfaces of structures, e.g., as sidewall coatings on gates in MOS devices for preventing shorting between silicon or silicided source and drain regions. Sidewall spacer coatings that are formed on the inside cavities have also been reported by others. For instance, U.S. Pat. No. 5,442,213 discloses a semiconductor device that has a high dielectric capacitor with sidewall spacers. A cavity embedded in a layer of a first dielectric material is initially provided with dielectric sidewalls and a conductive base. Sidewall spacers of a second dielectric material are then deposited to line the cavity""s original dielectric sidewalls. The spacers deposited are tapered such that they are thicker at the bottom and thinner at the top of the cavity. The objective for the sidewall spacers is to make it easier for the barrier and bottom electrode layers of the capacitor to be deposited on the substrate without leaving voids in the cavity.
U.S. Pat. No. 5,252,517 also discloses a method for isolating a conductive contact plug in a cavity from conductive elements that are embedded in the dielectric sidewalls of the cavity by lining the cavity with insulating sidewall spacers. The problem of misalignment tolerance is discussed in U.S. Pat. No. 5,471,094 which discloses a self-aligned via structure in which conductive plugs are embedded in a dielectric layer overlying a blanket metal layer M1. The M1 metal layer is then patterned by etching through the dielectric/M1 stack to produce a compound plug structure including the original plug material (in areas where the misaligned M1 via pattern mask overlapped with the original plug) and the dielectric material (in areas where the misaligned M1 via pattern mask overlapped with the dielectric material). However, none of these patents address the improvement of contact plugs by utilization of a dual diameter geometry wherein the misalignment-intolerant features may be reduced to sub-minimum lithography dimensions.
It is therefore an object of the present invention to produce a multi-diameter electrical conductor in a microelectronic structure that does not have the drawbacks and shortcomings of the conventional conductors fabricated in microelectronic structures.
It is another object of the present invention to provide a multi-diameter electrical conductor in a microelectronic structure that consists of a body portion that has a larger diameter and at least one neck portion that has a smaller diameter.
It is a further object of the present invention to provide a multi-diameter electrical conductor for use in a microelectronic structure that has a neck portion of the conductor formed in sub-minimum lithography dimensions defined by sidewall spacers.
It is another further object of the present invention to provide a method for forming a dual-diameter electrical conductor for use in a microelectronic structure that consists of a body portion that has a larger diameter and a neck portion that has a smaller diameter.
It is still another object of the present invention to provide a dual-diameter electrical conductor for use in a microelectronic structure which consists of a body portion that has a larger diameter formed integral with and substantially overlapping a neck portion that has a smaller diameter.
It is yet another object of the present invention to provide a dual-diameter electrical conductor for use in a microelectronic structure for connecting stacked capacitor electrodes and underlying circuit elements in semiconductor devices.
It is still another further object of the present invention to provide a method for forming a dual-diameter electrical conductor in a semiconductor device by first forming a body portion that has a larger diameter and then forming sidewall spacers in a contact hole such that a neck portion of a smaller diameter can be formed.
It is yet another further object of the present invention to provide a method for forming a dual-diameter electrical conductor for use in a semiconductor device by forming a body portion that has a larger diameter with a first conductive material unitarily with a neck portion that has a smaller diameter formed of a second conductive material that is substantially the same or different as the first conductive material.
In accordance with the present invention, a dual-diameter electrical conductor for use in a microelectronic structure and a method for its fabrication are provided.
In a preferred embodiment, a multi-diameter electrical conductor is provided which includes a body portion that has a first diameter, and at least one neck portion in contact with the body portion that has at least a second diameter smaller than the first diameter. The conductor may be fabricated with the body portion formed of a first conductive material and the at least one neck portion formed of a second conductive material. The electrical conductor may further be provided with an additional layer of a conductive material sandwiched between the body portion and the at least one neck portion, wherein the additional layer of conductive material is formed of a material different than that used in forming the body portion and the at least one neck portion. The additional layer of conductive material may have a diameter not less than the diameter of the neck portion and not more than the diameter of the body portion. The conductive material used in forming the body portion and the neck portion can be at least one member selected from doped polysilicon, refractory metals, metal silicides, low resistivity metals, noble metals and their alloys, metallic diffusion barrier materials, and oxide and nitride diffusion barrier materials. The low resistivity metals include Al, Alxe2x80x94Cu, Cu and Cu alloys, the metallic diffusion barrier materials include refractory metals, while the oxide, nitride and suicide diffusion barrier materials include TiN, TaSiN, TiAlN, WN, TaN and WSi. The electrical conductor formed can be advantageously used in a semiconductor device to provide electrical communication between an overlying electrode and an underlying circuit element. By utilizing the present invention novel method, the first diameter of the body portion can be substantially equal to a minimum lithographic dimension, while the second diameter of the neck portion can be less than the minimum lithographic dimension.
In another preferred embodiment, a dual-diameter electrical conductor is provided which includes a body portion that has a first diameter, and a neck portion in contact with the body portion that has a second diameter smaller than the first diameter. The body portion of the dual-diameter conductor substantially or completely overlaps the neck portion. The electrical conductor provides electrical communication between an electrode and a circuit element in a semiconductor device.
In another preferred embodiment, a microelectronic device that is fabricated with a dual-diameter electrical conductor therein is provided. The dual-diameter electrical conductor is constructed by a body portion that has a first diameter, and a neck portion in contact with the body portion that has a second diameter smaller than the first diameter.
In still another preferred embodiment, a dynamic random access memory device that is fabricated with a dual-diameter electrical conductor therein is provided. The dual-diameter electrical conductor in the DRAM device is constructed with a body portion that has a first diameter, and a neck portion in contact with the body portion that has a second diameter smaller than the first diameter. The memory device has at least one of its capacitor electrodes in electrical communication with the neck portion of the dual-diameter electrical conductor.
The present invention is further directed to a method for fabricating a dual-diameter electrical conductor that can be carried out by the operating steps of first providing a substrate that has a first conductive region, then depositing a layer of a first dielectric material on the substrate, then etching a first opening in the first dielectric material layer to expose the first conductive region in the substrate, then depositing a second conductive material into the first opening in the first dielectric material layer to form a body portion of the conductor, then removing a surface layer of the second conductive material to at least partially expose an upper sidewall surface in the first opening, then forming sidewall spacers of a second dielectric material on the upper sidewall surface of the first opening thereby defining a second opening through which the body portion of the conductor is exposed, and depositing a third conductive material into the second opening and forming a neck portion of the conductor that is in contact with the body portion of the conductor. The first opening in the first dielectric material layer can be advantageously formed by a reactive ion etching method. The first opening formed can be a contact hole that at least partially exposes the first conductive region in the substrate. The method may further include the steps of depositing and forming a stacked capacitor electrode on top of and in electrical communication with the neck portion of the electrical conductor. The sidewall spacers of the second dielectric material can be advantageously formed by a conformal deposition technique followed by an anisotropic etching process. The second opening defined by the sidewall spacers formed in the first opening is smaller than the first opening, thus allowing the formation of a neck portion of the electrical conductor having a diameter smaller than that of the body portion of the conductor.